When it comes to two-dimensional (2D) semiconducting materials, the potential advantages for developing ultra-thin and tunable electronic components are evident. However, one major challenge that researchers have faced is effectively interfacing these materials with gate dielectrics without creating interfacial traps that degrade transistor performance. A recent study by researchers at King Abdullah University of Science and Technology (KAUST) and Soochow University presented a new approach that could potentially lead to the fabrication of better performing transistors based on 2D semiconductors.
The proposed design outlined in a paper in Nature Electronics involves the use of hexagonal boron nitride (h-BN) dielectrics and metal gate electrodes with a high cohesive energy. Through their experiments, the researchers found that using platinum (Pt) as an anode resulted in the h-BN stack being less likely to trigger dielectric breakdown. This discovery led them to fabricate over 1,000 devices with chemical vapor deposited h-BN as dielectrics, demonstrating that h-BN gate dielectrics are best compatible with high cohesive energy metals such as Pt and tungsten (W).
To fabricate transistors with a vertical Pt/h-BN/MoS2 structure, the researchers cleaned a SiO2/Si substrate and patterned the source and drain electrodes using electron beam lithography. MoS2 was then transferred onto these electrodes to form the channel, followed by the transfer of CVD h-BN film over the structure. The Pt gate electrode was patterned using electron beam lithography and deposited using e-beam evaporation. This fabrication process resulted in a clean van der Waals interface between MoS2 and h-BN, improving reliability and performance of the transistor.
Contrary to the belief that CVD h-BN is a poor gate dielectric, the researchers found that selecting the right metal electrodes, such as Pt and W, enables its effective use in field-effect transistors with MoS2 channels. The clean van der Waals interface between MoS2 and h-BN enhances reliability and provides better gate control, showcasing the potential of this approach for 2D transistors.
The research team’s approach to fabricating 2D semiconductor-based transistors has shown promising results, reducing leakage currents and enabling a high dielectric strength of at least 25 MV cm-1. Tests revealed that Pt and W-based gate electrodes drastically reduced leakage current across h-BN dielectrics compared to gold (Au) electrodes. This advancement could pave the way for the development of highly performing 2D semiconductor-based devices and solid-state microelectronic circuits.
As the next step in their research, the team plans to develop ultra-small, fully 2D transistors to contribute to extending Moore’s Law. By exploring similar approaches and materials, other research groups may soon join the efforts to further enhance the performance and reliability of 2D semiconductor-based devices. The future of 2D transistor technology looks promising, with new advancements on the horizon that could revolutionize the electronics industry.
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